I am writing code for my ECE406 hwk 5 and have to write a test bench for a counter.

I need to simulate a clock signal to my counter module without have a billion statements in my initial block. my counter reg is 27 bits which would require 2^27 clock cycles , that would be a lot of manual clock changes

[Edited on March 1, 2007 at 12:18 AM. Reason : l]

3/1/2007 12:16:48 AM

406

3/1/2007 5:24:23 AM

reg clock;
always #5 clock = ~clock;



I haven't looked at verilog since I took 464 in Spring 2004, but looking back at some of my test cases, I always had the above code in my test cases.

also, do you have to check the value at every value? Why not check it every n'th clock cycle to see what the value of the counter is? Spot check at the first few cycles of the clock to see if the counter is going on, then at some specified points in the middle, and at the very end to see if the counter rolls over or whatever. You can match it all up on the signalscan after the simulation, or even print the values of the timer to the console.

3/1/2007 7:09:36 AM

yeah we only need to out put the high order bits [27:24]

3/1/2007 11:03:25 AM

i hated verilog, i had a shitty teacher plus was unmotivated

3/1/2007 3:34:47 PM

520 with Franzon was a great class

too bad no one hires Verilog programmers any more.

3/1/2007 11:59:21 PM